The FPGA design resource JD is as follows:
Responsibilities:
Design and implementation of FPGAs.
Participate in the architecture definition, implementation and verification phases.
Detailed design specification development.
Develop and implement block level RTL, perform synthesis and achieve timing closure.
Work with cross-functional teams (hardware, software, diagnostics and signal integrity groups).
Assist in complex subsystem level lab bring-up, integration, and unit test validation.
Desired technical skills:
Networking background
Experienced in designing with Xilinx, Altera and Microsemi FPGAs
Proficiency in HDL languages (Verilog, VHDL and System Verilog)
Hands on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART etc.
