TCS Virtual Interview_Formal Verification Engineer (RTL to Netlist / Netlist to Netlist)

Formal Verification Engineer (RTL to Netlist / Netlist to Netlist)\nExperience Range: 3 to 15+ Years\nLocation: Bangalore / Hyderabad / Noida / Ahmedabad/ Chennai/ Mumbai/ Pune\n\nRole Overview\nThe Formal Verification Engineer is responsible for ensuring functional equivalence and correctness of ASIC and SoC designs across design transformations such as RTL-to-Gate and Gate-to-Gate (ECO, DFT, low-power, CTS) flows. The role heavily uses formal equivalence checking and property-based formal verification to guarantee correctness without exhaustive simulation, working closely with RTL, DFT, STA, Physical Design, and Signoff teams to achieve first-pass silicon success.\n\nCore Responsibilities (All Levels)\nPerform formal equivalence checking (LEC) between RTL and synthesized netlists\nPerform Netlist-to-Netlist equivalence across ECO, DFT, low-power, and PnR iterations\nDebug and resolve non-equivalence points (NEPs) and failing cones\nHandle clock-gating, scan, and DFT-related equivalence challenges\nSupport UPF-aware and low-power formal verification\nCollaborate with cross-functional teams for signoff readiness\nDevelop scripts and automation to improve formal verification efficiency\n\nSenior Formal Verification Engineer – 3 to 5 Years\nExecute RTL-to-Gate LEC using Formality or Conformal under guidance\nSet up basic equivalence runs and constraints\nDebug simple mismatches such as reset differences and constant optimizations\nSupport ECO-related netlist equivalence checks\nGenerate equivalence reports and documentation\n\nLead Formal Verification Engineer – 6 to 9 Years\nOwn block or subsystem-level formal equivalence closure\nHandle complex non-equivalence issues due to clock-gating, scan insertion, and synthesis optimizations\nPerform Gate-to-Gate equivalence across multiple ECO iterations\nCreate and manage black-boxing, mapping rules, and formal constraints\nWork closely with RTL, DFT, and PD teams to close formal issues\nContribute to formal verification methodology and automation improvements\n\nMember Technical Staff / Principal Formal Verification Engineer – 10+ Years\nDefine formal verification strategy and signoff methodology for SoCs\nOwn SoC-level LEC signoff from RTL to final netlist\nResolve complex, late-stage equivalence failures across hierarchies and power domains\nDrive best practices, reusable FV flows, and signoff checklists\nMentor formal verification engineers and review signoff quality\nInterface with customers, internal signoff teams, and EDA vendors\n\nTools & Skills\nFormal Verification: Synopsys Formality, Cadence Conformal (LEC / Low Power)\nHDL: Verilog, SystemVerilog\nLow Power: UPF-aware formal verification\nDFT Awareness: Scan logic, clock-gating, test logic\nUnderstanding of synthesis, STA, and physical transformations\nScripting: Tcl (mandatory), Shell / Python (preferred)\n\nEducation\nB.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering\n\nRegards,\nPriyankha M