Physical Design Engineer

Role Overview\nThe Implementation (RTL to GDSII) Engineer is responsible for the complete physical design execution of ASIC and SoC designs, starting from RTL handoff to final GDSII tape-out. The role includes floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, physical verification, and signoff across advanced technology nodes. The engineer works closely with RTL, Design Verification, DFT, STA, and signoff teams to meet Power, Performance, Area, Thermal, Schedule (PPATS) targets.\n\nCore Responsibilities (All Levels)\nExecute end-to-end RTL to GDSII physical design flow for block, subsystem, and full-chip designs\nPerform floorplanning, power planning, placement, CTS, and routing\nDrive multi-corner multi-mode (MCMM) static timing analysis and closure\nEnsure physical verification signoff (DRC, LVS, ERC)\nAnalyze and close IR drop, EM, and signal integrity issues\nOptimize Power, Performance, Area, Thermal and Schedule (PPATS)\nSupport low-power implementation using UPF/CPF methodologies\nCollaborate with RTL, DV, DFT, STA, and signoff teams\nDevelop automation and improve RTL-to-GDSII methodologies\n\nSenior Implementation Engineer – 3 to 5 Years\nHandle block-level physical design under guidance\nPerform initial floorplanning, placement, CTS, and routing\nRun STA checks and identify setup and hold violations\nSupport timing ECOs and congestion fixes\nPerform basic physical verification (DRC, LVS)\n\nLead Implementation Engineer – 6 to 9 Years\nOwn block or subsystem-level RTL-to-GDSII implementation and closure\nDrive power planning, CTS strategy, and advanced timing closure\nPerform detailed MCMM timing analysis across all corners and modes\nResolve congestion, IR drop, and noise issues\nIntegrate DFT and low-power requirements into physical design\nSupport full-chip integration and tape-out readiness\n\nMember Technical Staff / Principal Implementation Engineer – 10+ Years\nDefine RTL-to-GDSII implementation strategy and signoff methodology for SoCs\nOwn full-chip physical design signoff and tape-out execution\nDrive PPA optimization on advanced nodes (7nm, 5nm, 3nm)\nLead late-stage timing, IR/EM, and noise issue resolution\nDevelop and standardize best practices, checklists, and automation frameworks\nMentor implementation engineers and provide technical leadership\nInterface with customers, foundries, and EDA vendors\n\nTools & Skills\nPhysical Design Tools: Synopsys Design Compiler, Fusion Compiler, ICC2\nCadence Tools: Genus, Innovus, Tempus\nTiming Analysis: Synopsys PrimeTime\nPhysical Verification: Siemens Calibre (DRC, LVS, ERC)\nPower & Reliability: IR drop, EM, noise analysis\nScripting: Tcl (mandatory), Perl, Python, Shell