Job Description
DFT Engineer\nExperience - 5+years\nLocation- Bangalore/Hyderabad\n\nExperience with Chip level DFT and Post Silicon debug / analysis\nUnderstanding of DFT architectures like :\nscan chain insertion and verification\nScan Compression Techniques\nJTAG\na. ATPG Pattern generation\nb. ATPG coverage analysis\nc.
Pattern simulation ( both timing/no timing)\nd. Pattern Retargeting\ne. Understanding JTAG/IJTAG\nf.
MBIST and Logic BIST\nProficient in writing SDC constructs for DFT modes\nProficient in Python, PERL/Shell script\nExcellent hands-on debug skills and problem-solving attitude.\nStrong Digital design concepts\nGenerating scan patterns and coverage statistics for various fault models like :\nstuck at, IDDQ,\nTransition faults, JTAG BSDL,\npattern generation for Memories (E-fuse etc.)
