Senior DFT Engineer

JOB DESCRIPTION\n\nPosition: Sr DFT Engineer (Lead)– ATPG & Scan Insertion\nExperience: 12–15 Years\nRole Overview\nWe are looking for a Senior DFT Engineer with deep expertise in ATPG and Scan Insertion to support high‑complexity SoC programs for our semiconductor clients. This role requires strong technical ownership across the DFT lifecycle and the ability to deliver manufacturing‑ready, high‑quality test solutions in a fast‑paced, multi‑stakeholder environment.\n\nKey Responsibilities\nLead DFT definition, implementation, and signoff for complex SoCs and IPs\nOwn Scan Insertion and Scan Compression strategies aligned with performance, area, and test cost goals\nDevelop, debug, and optimize ATPG patterns (stuck‑at, transition, at‑speed) to achieve high fault coverage\nPartner with client engineering teams across RTL, Synthesis, Physical Design, and Validation\nIdentify and resolve DFT/ATPG bottlenecks , including coverage gaps and pattern inefficiencies\nSupport silicon bring‑up , tester correlation, and customer test readiness milestones\nEnsure adherence to client DFT standards, schedules, and quality expectations\nProvide technical guidance and mentoring to junior DFT engineers on the project\n\nRequired Expertise\n10–12 years of hands‑on experience in DFT implementation and ATPG signoff\nStrong working knowledge of:\nScan architectures and scan compression methodologies\nFault models: stuck‑at, transition, path delay\nAt‑speed and timing‑aware ATPG\nPractical experience using leading commercial DFT tools (Synopsys, Cadence, or Siemens platforms)\nStrong understanding of RTL design flow, synthesis constraints, and timing concepts\nProven ability to work with large, multi‑site client teams and meet aggressive program milestones