NoC Verification Engineer

NoC Verification Engineer\n\nExperience : 7 to 14 Years\n\nKey Responsibilities:\nDevelop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.\nDefine and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.\nIntegrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and UCIe connected via NoC.\nModel and validate credit-based flow control, packet routing, QoS, and virtual channel behavior.\nPerform assertion-based verification (SVA/DVL) for protocol compliance and corner cases.\nDebug complex interactions at simulation or emulation level, including deadlocks, congestion, or ordering violations.\nWork closely with architects and RTL teams to align verification coverage and performance metrics.\nPerform coverage closure (code + functional) and ensure complete verification sign-off.\n\nRequired Skills:\nStrong experience with SystemVerilog, UVM, and object-oriented testbench development.\nIn-depth knowledge of NoC protocols (AXI4, CHI, TileLink, or proprietary NoC).\nVerification experience with coherent interconnects, cacheable traffic, and memory subsystem validation.\nFamiliarity with Synopsys, Cadence, or Siemens verification tools (VCS/Xcelium/Questa).\nFamiliarity with formal verification, assertions (SVA/PSL), and coverage metrics.\nAbility to debug low-level issues using waveform analysis, scoreboards, and transactors.\nFamiliarity with multi-core CPU, DSP, or GPU interconnect systems is a plus.\n\nLocation: Bangalore\n\nAbout Company:\nACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud.