Senior Principal RTL Design Engineer

Own micro-architecture, RTL development, quality reviews, and cross-functional coordination with verification, physical design, DFT, firmware, and architecture teams. Drive high-quality, reusable, and implementation-ready designs aligned to power, performance, and area targets.\n\nResponsibilities\n\nOwn end-to-end RTL design and development of SoC, subsystem, and IP blocks.\nTranslate architecture and product requirements into detailed micro-architecture and implementation plans.\nDevelop high-quality RTL in Verilog/SystemVerilog with focus on correctness, reusability, and scalability.\nLead design of key blocks such as interconnects, controllers, bridges, memory interfaces, datapaths, and control logic.\nDrive block-level and subsystem-level design integration and resolve interface, timing, and functionality issues.\nWork closely with verification teams to review test plans, support debug, and ensure design quality and closure.\nCollaborate with physical design teams on timing, power, area, clocking, reset, and synthesis constraints.\nSupport DFT, CDC, RDC, lint, low-power, and formal checks, and drive closure on design issues.\nReview specifications, micro-architecture documents, RTL, and design changes to ensure robustness and quality.\nAnalyze and resolve design bugs found in simulation, emulation, silicon bring-up, or customer use cases.\nMentor junior engineers and provide technical direction on coding practices, design quality, and methodology.\nContribute to design methodology improvements, reusable IP development, and automation initiatives.\n\nQualifications\n\nBachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or related field.\n10 to 16years of experience in digital design with strong exposure to IP, subsystem, and SoC development.\n\nRequired Skills\n\nStrong expertise in RTL design using Verilog/SystemVerilog.\nSolid understanding of digital design fundamentals, FSMs, pipelines, arbitration, buffering, and clock/reset design.\nStrong experience in micro-architecture definition and hardware implementation.\nGood understanding of AMBA protocols such as AXI, AHB, and APB.\nExperience in designing interconnects, bus fabrics, DMA, memory-mapped peripherals, control/data path logic, or protocol bridges.\nStrong debugging skills for simulation, synthesis, and integration issues.\nFamiliarity with lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power design flows.\nExposure to power, performance, and area optimization techniques.\nScripting experience in Python, Perl, Tcl, or Shell for automation and productivity improvements.\nStrong communication and cross-functional collaboration skills.\n\nPreferred Skills\n\nExperience with PCIe, DDR, NoC, cache/coherency, security, or safety-related designs.\nExposure to low-power design methodologies including UPF/CPF.\nExperience with formal verification support and silicon debug.\nExperience leading small design teams or owning major subsystems in large SoC programs.\n\nKey Competencies\n\nRTL and micro-architecture ownership\nSoC and subsystem integration\nTechnical leadership\nProblem solving and debug\nQuality and design closure focus\nMentoring and stakeholder collaboration