IP Design Verification Engineer - UVM | SoC | Embedded Processors
Job Description
&A1; Verify the Future of Intelligence — From Silicon to System
At Texas Instruments , our engineers don't just design chips — they ensure every line of RTL is functionally correct, verified, and ready to power the world's most demanding applications. If you're a verification expert who thrives on UVM methodology, SoC integration, and driving verification closure , this is your opportunity.
About the Role
We are looking for a talented IP Design Verification Engineer – UVM | SoC | Embedded Processors to join our Processors and Application Specific Microcontroller (ASM) Business Unit — part of TI's Embedded Processors group.
You will own the full DV lifecycle — from verification strategy and test plan creation to UVM testbench development, coverage closure, and SoC integration debug — for cutting-edge SoCs spanning 5nm technologies targeting automotive ADAS, zonal controllers, domain controllers, and industrial real-time control applications.
This is a high-ownership, high-impact role where your verification work directly ensures the functional correctness of TI's most advanced embedded processor designs.
Key Responsibilities
- Drive verification strategy and create comprehensive test plans for IP blocks and sub-systems
- Develop and enhance UVM and C-based testbenches and verification infrastructure
- Develop testcases for IP performance/throughput measurement and stress testing
- Triage regressions , debug simulations, and analyze coverage metrics
- Work with cross-functional teams to achieve full verification closure
- Participate in IP/sub-system specification activities and influence micro-architecture decisions
- Design and execute reusable verification methodologies
- Debug and resolve SoC integration issues in collaboration with SoC DV teams
- Achieve DV signoff using SV & UVM constrained random methodology:
- Develop UVM components: agents, drivers, monitors, and scoreboards
- Define and meet all functional coverage goals
- Achieve 100% code coverage (block, expression, toggle) at IP DV level
- Leverage AI-assisted verification tools for faster closure and signoff
