Formal Verification Engineer
Job Description
About the Company
Proxelera is a specialized semiconductor and system software engineering partner headquartered in Bengaluru. We provide end-to-end silicon design and productization services, focusing on high-quality IP design and complex verification for global clients. Our culture emphasizes technical excellence, mentorship, and driving the success of next-generation AI and networking silicon.
About the Role
We are seeking a Formal Verification Engineer with 5–8 years of experience to join our team in Bengaluru. You will lead connectivity and block-level property verification for Test Chips and DDRPHY using formal verification methodologies.
KEY RESPONSIBILITIES:
- Verification of Test Chips and DDRPHY: Connectivity verification for Test chips, Block level property verification for DDR PHY along with other use cases.
- Good understanding of Formal property verification, In-depth knowledge in formal verification algorithms, engines and use cases
- Proven expertise in system Verilog assertion and abstract model development
- Proven expertise in developing formal verification infrastructure for FPV, DPV, SEQ and other use cases is strongly preferred
- Contributes to test plan development.
- Language : System Verilog and SVA (System Verilog Assertions)
Qualifications
B.E./B.Tech or M.E./M.Tech in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), or VLSI Design.
Required Skills
Language: System Verilog ,Formal verification, FPV, DPV, SEQ System Verilog Assertions
