Field-Programmable Gate Arrays Engineer

The ideal candidate should have hands-on experience with FPGA tools, validation platforms, and high-speed interfaces. ️ Key Responsibilities '05; Design, implement, and verify FPGA-based solutions '05; Work on FPGA design flow including Synthesis, PNR & Timing Closure '05; Perform timing analysis and resolve timing-related challenges '05; Conduct simulations using Questasim '05; Debug hardware in lab environments using oscilloscopes & analyzers '05; Validate FPGA designs on hardware boards '05; Maintain and enhance technical documentation '05; Collaborate with cross-functional engineering teams Required Skills & Experience 5–10 years of FPGA Design & Validation experience, O-RAN Strong knowledge of FPGA tools: Libero / Vivado / Quartus Expertise in RTL Design (Verilog/VHDL) Experience with FPGA hardware platforms & board validation Hands-on experience in TCL scripting Good understanding of IPs like DDR, PCIe, Transceivers Experience with Questasim simulation tool Strong debugging skills using: Oscilloscopes Logic analyzers FPGA debuggers &99;️ Preferred Domain Experience '14;️ SDI / DisplayPort / HDMI 2.2 / SLVS '14;️ Motor Control / Holoscan '14;️ TSN (Time-Sensitive Networking) & Ethernet Protocols Interested candidates or references can share resumes at: