TCS Virtual Interview_Design Verification (DV) Engineer

Design Verification (DV) – Job Description\nExperience Range: 3 to 15+ Years\nLocation: Bangalore / Hyderabad / Noida / Ahmedabad/ Chennai/ Mumbai/ Pune\n\nRole Overview\nThe Design Verification (DV) Engineer is responsible for ensuring functional correctness, performance, and reliability of ASIC and SoC designs using coverage-driven verification methodologies. The role spans IP, subsystem, and full-chip verification using SystemVerilog/UVM, assertion-based verification, protocol verification, and power-aware simulation, working closely with RTL, Architecture, DFT, PD, and Silicon Validation teams.\nCore Responsibilities (All Levels)\nDevelop and execute verification plans aligned with design specifications\nDesign and implement UVM-based verification environments and testbenches\nCreate and run directed and constrained-random test cases\nAnalyze simulation results, debug failures, and report root causes\nCollect and close functional, code, and assertion coverage\nCollaborate with cross-functional teams to achieve first-pass silicon success\n\nSenior Design Verification Engineer – 3 to 5 Years\nPerform IP or block-level verification using SystemVerilog and UVM\nDevelop basic sequences, drivers, monitors, and scoreboards\nExecute regressions and debug functional failures\nWork on functional and code coverage collection\nAssist in assertion development and protocol checking\n\nLead Design Verification Engineer – 6 to 9 Years\nOwn IP or subsystem-level verification from plan to signoff\nArchitect reusable and scalable UVM environments and components\nDrive coverage-driven and constraint-random verification strategies\nPerform power-aware verification using UPF\nSupport gate-level simulations, CDC/RDC, and lint checks\nMentor junior engineers and review verification quality\n\nMember Technical Staff / Principal Design Verification Engineer – 10+ Years\nDefine verification architecture and strategy for full-chip SoCs\nOwn SoC-level verification execution and coverage signoff\nLead cross-IP, interconnect, and NoC verification\nDrive emulation, acceleration, and FPGA prototyping strategies\nMentor DV teams and influence verification methodology improvements\nInterface with customers and stakeholders for quality and delivery\n\nTools & Skills\nLanguages & Methodologies: SystemVerilog, UVM, SVA\nSimulators & Debug: VCS, Xcelium, Questa, Verdi\nCoverage: Functional, Code, Assertion Coverage\nProtocols: AMBA (AXI/AHB/APB), PCIe, USB, DDR, SPI, I2C, UART\nPower-Aware Verification: UPF-based simulation\nScripting: Python / Perl / Shell (preferred)\n\nEducation\nB.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering\n\nRegards,\nPriyankha M