Sr. Engineer/Staff Engineer, Design Verification,System IP
We are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure.
This role is hybrid , based out of Bangalore, India.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- You have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM.
- You enjoy debugging complex design and verification issues and working closely with cross-functional teams.
- You're comfortable building verification environments from scratch and driving coverage closure.
- You have familiarity with standard bus protocols and modern verification tools.
What We Need
- Experience owning block or subsystem-level verification from test planning to sign-off.
- Strong understanding of constrained-random verification, coverage analysis, and regression debugging.
- Familiarity with protocols such as AXI, ACE, CHI, or PCIe.
- Scripting experience in Python, Perl, TCL, or Bash for automation and workflow improvements.
What You Will Learn
- Verification of advanced CPU and memory-management related IPs used in AI/ML systems.
- Building scalable UVM environments and improving verification methodologies.
- Collaborating across architecture, RTL, and validation teams throughout the development cycle.
- Using Automation and AI-assisted tools to improve productivity and debug efficiency
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
