ASIC RTL Design Engineer

Position: ASIC RTL Design Engineer\n\nExperience: 8+ Years\n\nLocation: Noida\n\nShare resume on [email protected]\n\nKey Responsibilities\n\n- Develop synthesizable RTL from micro-architecture specifications.\n- Design digital blocks such as control logic, datapath, and bus interfaces (AXI/AHB/APB).\n- Debug and validate RTL using simulation and waveform analysis.\n- Collaborate with verification teams for functional validation.\n- Support RTL synthesis, timing closure, and integration at SoC level.\n- Maintain design documentation.\n\nRequired Skills\n\n- Strong digital design fundamentals.\n- Experience in Verilog/SystemVerilog RTL coding.\n- Knowledge of AMBA protocols (AXI/AHB/APB).\n- Familiarity with synthesis, lint, and CDC tools.\n\nGood debugging and problem-solving skills.