Senior Engineer - ASIC Design Verification

eInfochips services 7 of the top 10 semiconductor companies and is recognized by NASSCOM, Zinnov and Gartner as a leading Semiconductor service provider.\n\nROLE & RESPONSIBILITIES:\n\nAn expert level with developing UVM-based SV test-benches\nHighly experienced with defining block, sub-system and SOC top level test plans.\nRelevant experience with one or more of PCIe, NVMe, NAND, DDR and CPU sub-systems.\nDeep understanding and knowledge of verification methodologies, flows and quality metrics\nThe incumbent will be responsible for executing complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews, and close tracking of technical as well as management aspect\n\nESSENTIAL SKILLS & EXPERIENCE:\nAt-least 5 years of experience in System Verilog HVL.\nAt-least 3 year of experience in OVM/UVM/VMM/Test Harness.\nHands on experience of developing assertion, checkers, coverage and scenario creation.\nMust have executed at-least 1 SoC Verification project\nExperience in developing test and coverage plan, Verification environment and validation plan.\nKnowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.\n\nEDUCATION BACKGROUND:\nB.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.\n\nIf interested, please share your CV to\n\nShare the opportunity with your friends who are looking for a job opportunity !!!