STA Engineer

STA Engineer – 5+ Years Experience

We are seeking an experienced STA (Static Timing Analysis) Engineer with 5+ years of expertise in ASIC/SoC timing analysis and closure for advanced technology nodes. The ideal candidate should possess strong knowledge of timing methodologies, signoff flows, and timing convergence across full-chip and block-level designs.

Key Responsibilities

• Perform block-level and full-chip Static Timing Analysis (STA).
• Handle timing closure for setup, hold, recovery, and removal checks.
• Work on MMMC timing environments and timing signoff methodologies.
• Analyze and debug timing violations across different corners and modes.
• Collaborate closely with Physical Design, RTL, DFT, CTS, and ECO teams.
• Drive timing closure during synthesis, placement, CTS, and routing stages.
• Perform constraint validation and SDC generation/debugging.
• Support ECO implementation and timing verification.
• Analyze and resolve clock-domain crossing (CDC) and timing-related issues.
• Ensure timing signoff quality for tapeout readiness.

Required Skills

• Strong hands-on experience in:
• Static Timing Analysis
• Timing Closure
• MMMC setup
• Constraint development/debugging
• ECO timing fixes
• Expertise in tools such as:
• Synopsys PrimeTime
• Tempus
• ICC2 / Innovus (basic PD flow understanding)
• Good understanding of:
• Timing concepts
• Clock Tree Synthesis (CTS)
• OCV/AOCV/POCV
• SI and Crosstalk analysis
• Low-power timing checks
• Experience with advanced technology nodes such as 16nm/7nm/5nm is preferred.
• Scripting knowledge in Tcl/Perl/Python is an added advantage.

Qualification

• Bachelor's/Master's degree in Electronics/Electrical Engineering or related field.

Experience

• 5+ years of relevant experience in STA/Timing Closure.

Preferred Skills

• Exposure to full-chip timing signoff.
• Strong debugging and analytical skills.
• Good communication and cross-functional collaboration abilities.

Opportunity to work on high-performance SoC designs and advanced semiconductor technologies.