Design Verification Manager

You will also work with design team to make sure that high quality verification is achieved for first pass success of SoC. Location : Bangalore. Qualifications and Skillset Requirements Minimum BE/BS degree (Masters preferred) in Electrical/Electronics Engineering with 12 years of practical experience Strong fundamentals in digital ASIC design and verification Experience in leading and managing the design verification team Strong in DV Methodology and process Must be Technically hands on Familiarity with AMBA bus protocols, system memory hierarchy, system debug infrastructure and multi-core SOC Strong experience with Verilog, System Verilog, UVM and/or other Expertise in ARM cores and related infrastructure (like Coresight, NIC/NOC, other bus interconnects etc.) is highly desirable Understanding of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, UART and experience in SSD is highly desirable Understanding of IP designs and verification requirements Understanding of Gate Level Simulations (GLS) with timing and related debug capability Excellent communication and leadership quality to technically mentor and lead a team of verification engineers Roles And Responsibilities Lead and Manage DV team Define and develop verification architecture, methodology, environment and test plans driven by functional coverage Hands on contribute to IP and SoC verification, process and environment creation Work closely with design team for continuous improvement of design quality through verification Review the test plans, verification tests and coverage for other team members Mentor team members for technical growth in verification Establish process of verification and quality improvements Contribute on GLS, emulation, FPGA based and Post Si validation