Senior Engineer Design Automation, Scribe Design Non-Array

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Micron Technology’s vision is to transform how the world uses information to enrich life and our dedication to people, innovation, tenacity, teamwork, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community. We are the only company manufacturing today's major memory and storage technologies: DRAM, NAND and Emerging memory.

We are looking for an energetic, ambitious, result-driven individual with strong work ethic and integrity to join us as the Scribe Design Engineer. The Scribe Design Non-Array (SDNA) team is responsible for the design, layout, and verification of CMOS electrical test structures that enable CMOS device development, Compact modeling, Reliability modeling and Fab process monitoring.

In this role you will work with a group of Engineers in India, Japan, and the US. As part of a global team, you will contribute to physical layout, floor planning and verifying through DRC and in-house verification tools. This role will allow you to work on all technology types at Micron.

Responsibilities and Tasks include, but are not limited to:

• Proactively identify problem areas for improvement, propose, and develop innovative solutions.
• Continuously evaluate and implement new tools and technologies to improve the current automation flows.
• Demonstrate growth mindset and work towards submitting patent disclosures and research papers.
• Provide guidance and mentorship to junior members of the team.

Qualifications:

• Advanced understanding of EDA tools and CAD flows.
• Develop and enable programmatically defined P-cell (Parameterized layout generator) devices for CMOS modules.
• Implement advanced methodologies for schematic automation using SKILL/SKILL++ which can be scalable between technologies and enhance design workflow
• Implement advanced methodologies for layout automation using SKILL/SKILL++ which can be scalable between technologies and enhance design workflow.Generating the DUT using PCELL based on the requirementFloorplan & Placement of DeviceWiring of the DUT to the PAD's
• Deep knowledge of Python to handle data processing and tool enhancements.
• Good understanding of programming fundamentals and exposure to various programming languages including: Skill/Skill++ (Cadence), Perl, Python, Tcl.
• Good understanding of basic CMOS process manufacturing ,layout design rules and layout design.
• Working knowledge of Linux is a must.
• Excellent problem-solving skills with attention to detail.
• Ability to work in a dynamic environment.
• Proficiency in working effectively with global teams and stakeholders.
• 5+ years of relevant experience.

Education:

• A Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering or Electronics Engineering.