Senior RTL Design Engineer

We are looking for an RTL Design Engineer (5-7 years' experience) to join our Data Center Connectivity design team. This role is ideal for engineers passionate about RTL, microarchitecture, interconnect logic, and front-end design flows driving high-bandwidth, low-latency systems.

Key Responsibilities

• Take ownership of RTL design and microarchitecture for IP/Subsystems.
• Work from high-level architectural specs and break them down into detailed microarchitecture and build synthesizable RTL from scratch.
• Design efficient Datapath and control logic - think queues, arbiters, FIFOs, and clock-domain crossings - that can scale for high bandwidth and low latency.
• Collaborate closely with architects, and SoC level cross functional teams to make sure the design meets performance, power, and area goals.
• Write clear and maintainable System Verilog RTL and documentation that others can build on.
• Drive the full front-end design flow - lint, CDC, synthesis, timing, and debug - and own your block through to tape out.
• Participate in design reviews, contribute ideas to improve logic architecture, and help refine design best practices.
• Debug simulation or synthesis issues quickly and efficiently and work hands-on with verification teams to close all functional coverage.
• Stay up to date on new interconnect technologies and help shape next-gen architecture discussions.

Required Skills and Experience

• E./B. Tech/M. E/M. Tech in Electrical, Electronics, or Computer Engineering.
• 4-7 years of strong hands-on RTL design and integration experience in SoC, networking, or interconnect logic.
• Proven strength in microarchitecture development and System Verilog/Verilog RTL coding.
• Good understanding of connectivity and interconnect protocols such as AMBA (AXI/AHB/APB) etc; PCIe, or Ethernet is a plus.
• ARM/RISC-V processor-based subsystem/SoC knowledge is a plus.
• Solid understanding of clock/reset architectures, FIFOs, CDC, and low-power design techniques.
• Hands on writing in SDC and UPF constraint writing, LEC.
• Hands-on expertise with front-end industry EDA tools.
• Strong debugging and analytical skills with experience in Git and collaborative design workflows.

Why This Role

• Work on next-gen data center connectivity.
• Gain deep exposure to microarchitecture, connectivity subsystems, and SoC Design integration.
• Be part of a highly technical team that values innovation, ownership, and learning.
• Competitive compensation, technical growth, and exposure to cutting-edge design challenges.