Design Verification Engineer

Responsibilities & Desired skills:
Construct SoC level test benches using verification components developed at the block/IP level. Test bench
architecture for random/directed testing, stimulus generation, and checking to include custom and off the
shelf VIP/UVCs.
Develop and execute SoC verification plans focused on IP block interoperability and SOC/System level.
Develop and execute verification plans based on design specifications and collaboration with architects and
designers.
Verify SoC using advanced verification methodologies
Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and
Debug use-cases.
Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modeling
(TLM), HW emulation/acceleration, and SW driven verification.
Work with design team to understand design intent and bring up verification plans and schedules
You will think through design corner cases and be able to write relevant cover points
Debug test cases and report verification results to achieve expected code/functional coverage goal. Utilize
constrained random verification, functional coverage, code coverage and assertions to achieve goals.
Assist in emulation, FPGA, prototyping efforts.
Implement / maintain automated verification flows in languages such as Python / Shell scripts.
5+ years of verification experience is required