Principal Engineer, Analog Mixed-Signal IC Layout
Job Overview:
As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout.
You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who thrives in a collaborative environment.
Basic Qualifications:
- Bachelor's degree or advanced diploma in Electrical Engineering (EE)
Required Experience:
- 10+ years of experience in high-speed analog IC layout using Cadence Virtuoso
- Prior experience with BiCMOS layout is strongly preferred
- Proven experience handling at least one chip top-level through tapeout
- Proficiency in layout extraction and parasitic analysis for high-speed circuits
- Awareness of EMIR and antenna DRC rule-compliant layout practices
- Experience with Cadence SKILL and TCL scripting is highly recommended
