Posted 14 June, 2026
Lead analog mixed signal verification engineer
Ciliconchip
Vijayapura, KA, IN
Full Time
Reference: ef809aa62dfe82c7
Job Description
Roles & Responsibilities:
Run and debug SPICE-based and digital simulations for AMS/So C IPs and subsystems.
Understand analog and digital design intent, review simulation setups, and ensure correct test conditions.
Analyze results using waveform/debug tools and identify root cause for functional mismatches.
Work with designers to resolve analog/digital interface issues, model issues, and corner-case failures.
Use simulation and waveform tools to speed up debug and improve verification turnaround time.
Contribute to improving simulation workflows (run scripts, log parsing, automation, regression stability).
Support mixed domain / co-simulation activities where applicable (e.g., SPICE + digital).
Document verification findings, debug notes, and simulation methodology updates.
Supervise, train, lead small team of 5 to 10 engineers
Required Qualifications:
5 to 8 years of relevant experience in AMS verification / simulation / debug.
Strong fundamentals of Analog and Digital concepts. Good working knowledge of Verilog / System Verilog concepts (test/control, connectivity, modeling).
Hands-on experience with SPICE and digital simulation tools and debug environments.
Ability to understand simulation environments and debug analog/digital design-related issues.
Comfortable working in a collaborative team setup with clear communication.
Tools & Environment:
Analog/Custom: Virtuoso, Prime Sim, Fine Sim, HSPICE
Digital Simulation & Debug: Xcelium, Sim Vision
Waveform/Analysis: Wave View (or equivalent)
AMS verification Tools (Synopsys XA, Cadence Discovery AMS)
Run and debug SPICE-based and digital simulations for AMS/So C IPs and subsystems.
Understand analog and digital design intent, review simulation setups, and ensure correct test conditions.
Analyze results using waveform/debug tools and identify root cause for functional mismatches.
Work with designers to resolve analog/digital interface issues, model issues, and corner-case failures.
Use simulation and waveform tools to speed up debug and improve verification turnaround time.
Contribute to improving simulation workflows (run scripts, log parsing, automation, regression stability).
Support mixed domain / co-simulation activities where applicable (e.g., SPICE + digital).
Document verification findings, debug notes, and simulation methodology updates.
Supervise, train, lead small team of 5 to 10 engineers
Required Qualifications:
5 to 8 years of relevant experience in AMS verification / simulation / debug.
Strong fundamentals of Analog and Digital concepts. Good working knowledge of Verilog / System Verilog concepts (test/control, connectivity, modeling).
Hands-on experience with SPICE and digital simulation tools and debug environments.
Ability to understand simulation environments and debug analog/digital design-related issues.
Comfortable working in a collaborative team setup with clear communication.
Tools & Environment:
Analog/Custom: Virtuoso, Prime Sim, Fine Sim, HSPICE
Digital Simulation & Debug: Xcelium, Sim Vision
Waveform/Analysis: Wave View (or equivalent)
AMS verification Tools (Synopsys XA, Cadence Discovery AMS)
