Senior Staff Analog Design Enginee

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished analog design engineer with a passion for driving innovation in high-speed memory interface technologies. With 8-15 years of experience, you have mastered the fundamentals of analog design and device physics, and you thrive in environments that challenge you to push the boundaries of what is possible. Your expertise in high-speed IO designs, especially in advanced process technologies like CMOS, FinFET, and GAA, positions you as a technical leader. You are motivated by the opportunity to lead and mentor teams, guiding them to deliver best-in-class products that set industry benchmarks for performance and reliability.

You possess a deep understanding of JEDEC requirements and standards for memory interfaces, making you a trusted authority in the development of DDR, HBM, and UCIe PHY IPs. Your knowledge of ESD and reliability concepts ensures robust designs, while your familiarity with signal and power integrity further strengthens your technical arsenal. Communication is your forte; you articulate complex ideas clearly and collaborate effectively across global, cross-functional teams. You are as comfortable in technical discussions as you are in strategic planning, always advocating for quality and innovation.

You value inclusivity and thrive in a diverse, collaborative workspace. You are driven by curiosity, always seeking new solutions and technologies, and you approach challenges with resilience and adaptability. Your leadership inspires others to reach their full potential, and you are committed to continuous learning and professional growth.

What You'll Be Doing:

• Leading the design and development of next-generation high-speed memory interface PHY IPs, including DDR, HBM, and UCIe.
• Driving innovation in high-speed IO circuit designs for memory interfaces using advanced process technologies (CMOS, FinFET, GAA).
• Collaborating with global cross-functional teams-including digital, verification, and layout engineers-to deliver integrated solutions.
• Applying analog design fundamentals and device physics expertise to optimize performance, power, and area of memory interface circuits.
• Ensuring compliance with JEDEC standards and requirements, contributing to industry-leading reliability and robustness.
• Mentoring and guiding design teams to achieve quality milestones, fostering a culture of technical excellence and continuous improvement.
• Participating in design reviews, providing technical leadership and constructive feedback to peers and junior engineers.
• Supporting product integration and validation, troubleshooting issues, and optimizing designs for manufacturability and scalability.

The Impact You Will Have:

• Accelerate the development of cutting-edge memory interface solutions, advancing Synopsys' leadership in semiconductor IP.
• Enable customers to build faster, more reliable, and energy-efficient silicon chips for applications ranging from AI to data centers.
• Shape industry standards by ensuring compliance and contributing to the evolution of JEDEC and related protocols.
• Drive technical innovation, introducing new architectures and methodologies that transform high-speed IO design.
• Mentor and elevate the capabilities of the engineering team, fostering a collaborative and high-performance culture.
• Deliver robust products with exceptional signal and power integrity, setting benchmarks for quality and reliability.
• Strengthen Synopsys' reputation as the go-to provider for advanced memory interface IPs.
• Contribute to the global engineering community through technical presentations, publications, and cross-team knowledge sharing.

What You'll Need:

• BTech/MTech in Electrical Engineering, Electronics, or related field.
• 8-15 years of hands-on experience in analog circuit design, with a focus on high-speed IO for memory interfaces.
• Expertise in advanced semiconductor process technologies (CMOS, FinFET, GAA).
• Strong understanding of device physics, ESD protection, and reliability engineering.
• Knowledge of JEDEC standards (DDR, HBM, UCIe) and memory interface protocols.
• Experience with signal integrity and/or power integrity analysis and mitigation strategies.
• Proficiency in design tools and simulation environments for analog/mixed-signal circuits.