Senior DV Engineer

LTTS is hiring for Design Verification Engineers with 5+ Years of experience.\nJob Location : Bangalore, India\nDetailed JD is as below ::\nJob Description DV Positions:\nDefine and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification\nDevelop functional tests based on verification test plan\nDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage\nDebug, root-cause and resolve functional failures in the design, partnering with the Design team\n\nQualifications and Skills for DV Positions:\nBachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience\n5 + of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification\n5+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies\nExperience in development of UVM based verification environments from scratch\nExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycle\nExperience with verification of ARM/RISC-V based CPU sub-stems or SoCs\nExperience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet\nExperience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments\nExperience with revision control stems like Mercurial(Hg), Git or SVN