Hiring AI/ML SW, FW and Si Design, DV Engineers (Bangalore, Bay Area CA)

Expertise in Model optimization with quantization, pruning, distillation or mixed-precision inference. Practical knowledge of inference engines (vLLM, llama.cpp, ONNX Runtime). Experience in deploying large models locally or on edge devices with limited memory/compute constraints.\n\nAI Applications Engineer with full-stack web application development experience, including proficiency in Front-end frameworks (React, Netx.js,Svelte) and Backend experience with Python(FastAPI/Flask),Node.js, Rust.

Experience with interfacing with AI/ML backend via REST or gRPC APIs. Experience building apps that integrate LLMs, text-to-image, or speech models. Familiarity with multimodal data handling - audio/video streaming, file parsing, camera/mic APIs\n\nDevOps/Edge AI Engineer strong background in Linux systems engineering and containerization (Docker, Podman, LXC). Experience in deploying AI Inference Services locally or at the edge (llama.cpp, ollama, vLLM, ONNX). Experience with embedded systems or edge AI devices (e.g., Jetson, Coral).

Solid understanding of Networking, Security, and firewall configurations for local appliances.\n\nSystem SW and Firmware Engineers (multiple positions available)\nSystems Security(SW) Engineer with strong knowledge and hands-on experience with Linux Kernel and User space security aspects; Trusted firmware, Secure Boot, Boot loader, Crypto co-processors e.g. CMRT (Root of Trust).\nSystems Platform Engineer with strong knowledge of Linux kernels, IPC/System V, POSIX libraries, multi-threaded SW and process management.\nSystems Engineer with experience in writing device driver for Memory, Control Plane and Cluster Management, with excellent knowledge of Linux kernels, IPC/System V, Memory management and distributed systems, Linux High availability, and NUMA.\nSystems SW Engineer with experience in developing health monitoring, Linux drivers, and memory checker debug frameworks.\nSystems SW Engineer with Experience in cluster management software and device discovery protocols like PAXOS, NCCL, RCCL, or any other distributed device discovery\nFirmware Engineer with experience in writing device drivers for RDMA, RoCE v2, Ethernet, CXL, and other proprietary interfaces.\n\nRTL Design Engineers\nHands-on experience with micro-architecture and RTL development of ARM CPU Processors or high-speed custom ASICs/Accelerators .\nRTL design expertise w ith any one of - Cache controllers, IO interfaces (PCIe, CXL, Ethernet), UCIe, Memory Controllers, Display, and Video Encoding/Transcoding IP designs .\n\nDesign Verification Engineers (Multiple positions available under each domain)\n· Deep expertise and hands-on experience in developing UVM, SV testbench components, Checkers, Scoreboard and Stimulus with 5yr+ experience in IP/sub-system or SoC level verification.\n· Experience in defining test plans and developing directed/constrained random tests to achieve Coverag e\nSoC DV with focus on system bring-up, infrastructure correctness, and debug/interrupt subsystems. Full-chip and multi-chiplet with real-silicon mindset verification.

Multiple positions available for candidates with PCIe/CXL flows, host-device coherency interactions, DMA engines and UCIe.\nDV Infrastructure: Strong hands-on experience in setup and automation of regression test suites for simulation and emulation domains. Proficiency with Git branching, Release Management and CI/CD , Makefiles , scripting and familiarity with UVM methods. Preferred experience with Siemens EDA tools.\nCPU: Strong Arch knowledge in ARM Subsystems(CPUSS), including CMN, SMMU, Coherency, CHI\nLPDDR5 : Strong knowledge and hands-on experience in LPDDR5 protocol knowledge of DDR/DFI, Memory Compliance testing\nUCIe : Expertise and hands-on experience with UCIe verification, including FDI/RDI concepts.\nNetwork and Memory Encryption : Strong domain expertise in Memory Encryption/Decryption (AES-XTS) and Ethernet MACSec\nEthernet : Strong Arch knowledge in Ethernet domain including Controller, Serdes for various port modes and speeds\nPCIe/CXL : Strong domain knowledge in latest generation of PCIE and CXL protocols, PIPE, serdes\nPrior experience and knowledge of APB/AXI/CHI bus protocols, Serial peripherals (eg: I2C, SPI)\n\nFPGA Prototyping (Platform) Lead\n· I n this role you will develop FPGA protypes for Tsavorite's Chiplets and SOC using commercially available FPGA prototype platforms/tools\n· Experience in handling RTL-to-Bitstream design cycle on million+ gate FPGAs\n· Hands-on experience wiwth design partitioning, Verilog coding for FPGA fit.\n· Expertise in timing analysis, design optimization for timing convergence and resource utilization\n· Familiarity with Intel/Altera Quartus or AMD Vivado design flows\n· Expertise in handling standard debugging tools such as ChipScope or custom debug tools\nPreferred Experience : Expertise in configuring and bringing up HardIP/embedded ARM Cores.\n· FPGA Design experience with any High Speed IO Protocols (PICe, Ethernet,CXL), configuring and bringup of Softcore Processor Microblaze (Xilinx) or Nios (Altera)