RTL (ASIC) Design Engineer

RTL Design Engineer (SDC Constraints)\n\n: +\n:\n: /\n\nWe are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise in RTL design, timing constraints, and close collaboration with synthesis and STA teams.\n\n'96; Design and develop RTL (Verilog/SystemVerilog) for complex ASIC blocks and subsystems\n'96; Create, review, and maintain SDC constraints (clock definitions, I/O constraints, false paths, multicycle paths, exceptions, etc.)\n'96; Work closely with synthesis, STA, physical design, and verification teams to achieve timing closure\n'96; Perform RTL quality checks, linting, and CDC analysis\n'96; Support timing debugging and constraint optimization across multiple design iterations\n'96; Participate in architecture discussions and design reviews\n'96; Ensure deliverables meet performance, power, and area (PPA) goals.\n\n'05; &\n%AA;️ 7+ years of hands-on experience in RTL ASIC design\n%AA;️ Strong and mandatory expertise in SDC\n%AA;️ Clocking strategies\n%AA;️ Timing exceptions\n%AA;️ Constraint validation and debug\n%AA;️ Proficiency in Verilog/SystemVerilog\n%AA;️ Solid understanding of ASIC design flow (RTL → Synthesis → STA → P&R)\n%AA;️ Experience working with Synopsys tools (DC, PrimeTime – preferred)\n%AA;️ Strong knowledge of timing concepts and timing closure\n%AA;️ Excellent debugging and problem-solving skills\n\nExperience in low-power design techniques\nExposure to CDC/RDC methodologies\nExperience with complex SoC designs\nScripting knowledge (Tcl / Perl / Python)\nPrior experience working with global or distributed teams