DFT Architect

EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\n\nDFT architect -14-18 years\n\nDeveloping silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.\n\nAs the Design for Test (DFT) Architect, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.\n\nKey Responsibilities\nArchitectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, and MBIST.\n\nEdge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.\n\nImplementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Logic BIST.\n\nCross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact.\n\nPost-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.\n\nTechnical Requirements\nExperience: 14-18 years in DFT, with at least 2 years in a leadership or principal role.\n\nTools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).\n\nMemory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities and boundary scan (IEEE 1149.1/6).\n\nAdvanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).\n\nLow Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.\n\nContact\nUday\n\nMulya Technologies\n\"Mining the Knowledge Community\"