Senior Design Engineer

Location: Bay Area, California (Onsite at Client Location)

Work Mode: Full-Time | Work From Office (WFO)

Work Authorization: Valid US Work Visa Required

About the Role

We are looking for an experienced Senior Design Engineer with strong expertise in SoC architecture, RTL development, and high-performance interconnects. The ideal candidate will play a key role in designing next-generation semiconductor solutions for cutting-edge compute and connectivity platforms.

Experience

'05; 8–12 Years of Industry Experience

Key Responsibilities

RTL Design & Development

Design and develop synthesizable RTL for:

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• AMBA AXI4 / AXI5 Interconnects
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• AMBA ACE & CHI Coherent Interfaces
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• DMA Engines
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• Protocol Bridges & Converters
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• Buffering Structures
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• Memory Subsystems interfacing with LPDDR4 / LPDDR5 / LPDDR5X Controllers
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• PCIe Endpoint, Root Complex, and Subsystem Integration Logic
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Microarchitecture Development

Define and implement microarchitecture for:

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• Transaction Ordering
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• QoS & Arbitration Schemes
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• Cache Coherency Mechanisms
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• Flow Control & Protocol Compliance
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• CDC (Clock Domain Crossing)
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• RDC (Reset Domain Crossing)
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Cross-Functional Collaboration

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• Translate system requirements into detailed microarchitecture specifications.
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• Work closely with architects and verification teams.
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• Develop test plans, coverage strategies, assertions, and protocol compliance checks.
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• Support SoC integration, performance tuning, and silicon bring-up activities.
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Performance & Implementation Support

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• Analyze and optimize latency, throughput, and power efficiency.
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• Support synthesis, timing closure, and physical design teams throughout implementation.
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Preferred Skills

'14; Strong RTL coding experience in Verilog/System Verilog

'14; Deep understanding of AXI, ACE, CHI, PCIe, and memory subsystem architectures

'14; Experience with high-performance SoC design and integration

'14; Knowledge of CDC/RDC methodologies and verification concepts

'14; Familiarity with synthesis and timing closure flows

Why Join?

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• Opportunity to work on advanced SoC and semiconductor products
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• Exposure to cutting-edge interconnect and memory technologies
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• Collaborative environment with leading architects and engineering teams
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EMAIL : [email protected]

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