Technical Lead-Central Design Methodology (CDM) Team

Job Title: Technical Lead - Central Design Methodology (CDM) Team Location: Bangalore Exp: 15+ yrs We are seeking an experienced and highly motivated Technical Lead to spearhead the Central Design Methodology (CDM) Team to drive the development, deployment, and continuous improvement of R&D organization’s design (EDA/CAD) methodologies and processes for IP and SoC development across Analog/Mixed-Signal (AMS), Digital, and RF design domains . This role is pivotal in defining, developing, and deploying cutting-edge tools, flows, recipes, methodologies, design-processes, gate-checklist that improve PPA , design efficiency and productivity, quality, reuse, robustness and time-to-market across multiple product lines. This role requires deep technical expertise in semiconductor Chip design methodologies, strong leadership skills, and the ability to collaborate effectively with R&D design functions/components (AMS, Digital, RF, PD, DV, DFT, Emulation/Validation) and EDA vendors. Key Responsibilities Methodology & Process Leadership and Strategy Define and execute the roadmap for design (EDA/CAD) tools, flows, recipes, methodologies, design-processes covering Analog, Mixed-Signal, Digital, and RF IP and SoC development. Collaborate with R&D design functions/components (AMS, Digital, RF, PD, DV, DFT, Emulation/Validation) to align methodologies with organizational goals. Establish standardized baseline for design, verification, implementation, signoff, release processes and quality gate-checklist across R&D design functions/components. And drive continuous improvement from that. Drive methodology adoption and ensure alignment with organizational quality, reliability, productivity and schedule goals. Lead the evaluation, bring-in and deployment of next-generation design technologies and new capabilities, automation solutions, and AI-assisted engineering workflows. Design Flow, Methodology and Process Development Architect, implement and maintain standardized and scalable end-to-end Chip design flows for: Analog and Mixed-Signal design Digital front-end and back-end design and implementation RF design and integration DFT design and integration IP development, reuse and manage Full-chip SoC integration Verification, Emulation/Validation Develop process for quality gate-checklist, signoff and design release (cross-functional design hands-off). Evaluate and integrate EDA tools, automation frameworks, scripting solutions. Establish flow interoperability across multiple EDA platforms and foundry technologies. Establish best practices for design reuse, verification, release and signoff. Automation and Infrastructure Lead the development of automation frameworks, scripts, and infrastructure to improve engineering efficiency. Drive implementation of reusable design kits, PDK integration methodologies, verification environments, and regression systems. Develop dashboards, metrics, and analytics to measure design quality, productivity, and methodology compliance. Cross-Functional Collaboration Partner and closely work with R&D Design Functions/Components (AMS, Digital, RF, PD, DFT, DV, Emulation/Validation) to develop their TFM, Recipe and Design-process and PPA push. Work closely with EDA vendors and foundry partners to influence tool capabilities and resolve methodology challenges. Support project teams during methodology & process deployment, training, and issue resolution. Ensure seamless integration of analog, mixed-signal and digital IPs into complex SoCs. Innovation & Continuous Improvement Stay ahead of industry trends in semiconductor design methodologies. Drive adoption of advanced techniques such as machine learning–based design optimization, cloud-enabled design environments, and AI-assisted verification. Champion efficiency improvements in design cycle time, PPA and quality metrics. Key Success Metrics Improved PPA of the Chips (IP/SoC). Improved design productivity and reduced development cycle time. Increased IP reuse and methodology adoption across projects. Enhanced first-pass silicon success rate. Reduction in design and verification turnaround time. Improved design quality and signoff robustness. Successful deployment of automation and methodology innovations. Team growth, engagement, and technical excellence. Required Qualifications Technical Skills Strong understanding of: Analog and Mixed-Signal design, verification and signoff tool, flow, methodologies (TFM) and design-process Digital design, verification and signoff TFM and design-process RF design, verification and signoff TFM and design-process Design-for-Test (DFT) TFM IP qualification, reuse, release and management frameworks Hands-on expertise in EDA tools (Cadence, Synopsys, Mentor, etc.) and scripting (Python, TCL, Perl). Proven track record in IP and SoC development methodologies and processes from concept to silicon. Experience with documentation & issue tracking process (Confluence/JIRA), revision control systems (LSF), workflow automation, and large-scale compute (HPC) environments. Education & Experience Master’s or Ph.D. in Electrical Engineering, Electronics, Computer Engineering or related field . 15+ years of experience in semiconductor design methodologies & processes with exposure to AMS, Digital, and RF domains. 5+ years of experience leading methodology, EDA, CAD, design enablement, or related technical teams. Excellent leadership, communication, and collaboration skills. Preferred Qualifications Experience in developing Central CAD Methodologies for large design organizations. Knowledge of advanced process nodes (FinFET, RF CMOS, SiC, GAN/GAS, etc.). Familiarity with AI/ML applications in EDA.