Job Description
Job Title: RTL Design Engineers
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Exp Level: 2-3 yrs
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Loctaion: Hyderabad
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Job Description:
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\n - Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog.
\n - Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams.
\n - Requires strong fundamentals in digital design, timing closure, and understanding of the ASIC flow.
\n - You'll debug simulation failures, implement ECOs, and support gate-level simulations.
\n - Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tapeout goals.
\n - Bachelor's or Master's degree in engineering in EE/CS is essential, along with 2-3 years of relevant experience.
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