SOC Verification, Sr Engineer

Job Title:

• SOC Verification - Sr. Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the last few years deep in verification, and you know the difference between a test plan that looks good in a review and one that actually catches the bugs that matter. You think in layers, from block-level checks to full SOC integration, and you understand that the hardest problems are usually the ones hiding at the boundaries between subsystems.

You are comfortable sitting with a design spec, asking the questions no one else thought to ask, and building a verification strategy that does not just check boxes but actually proves the design works. You do not wait for perfect clarity. You work with architects and designers to fill in the gaps, and you move forward with what you know while staying alert to what you do not.

Debugging energizes you. When a simulation fails at 3 a.m. in a regression run, you are the person who digs into waveforms, traces signals across clock domains, and finds the root cause, not just the symptom. You have written SystemVerilog testbenches, integrated third-party VIPs, and probably cursed at UVM more than once, but you also know it is the right tool for the job.

At Synopsys, you will work on real customer SOCs, not internal demos. The designs are complex, the stakes are high, and what you verify will ship.

What You'll Be Doing

• Build verification test plans from design specs for processor-based SOCs, defining scope, coverage goals, and test scenarios that map to real-world use cases
• Develop and maintain SystemVerilog testbenches and UVM environments, integrating Synopsys VIPs and third-party verification IP for protocols like AXI, USB, PCIe, and MIPI
• Write and analyze SystemVerilog assertions and track code, toggle, and functional coverage to close verification gaps before tapeout
• Debug complex simulation failures across multi-clock-domain SOC designs using VCS, waveform viewers, and scripting to isolate root causes
• Mentor junior verification engineers through design bring-up, testbench architecture decisions, and debugging sessions
• Collaborate with architects, RTL designers, and post-silicon teams to align verification strategy with design intent and silicon validation plans
• Script automation flows using shell, Makefile, and Perl to improve regression efficiency and testbench reusability

The Impact You Will Have

• Catch critical design bugs before tapeout, reducing costly silicon respins and accelerating time to market for customer products
• Deliver verified SOC IP and subsystems that power high-performance computing, automotive, and aerospace applications used by industry leaders and startups alike
• Raise the quality bar for verification methodology across the team by introducing best practices, reusable components, and coverage-driven approaches
• Enable faster customer success by working directly on service projects that solve real customer SOC challenges using Synopsys EDA tools and IP
• Shape the skills and careers of junior engineers through hands-on mentorship, code reviews, and collaborative problem-solving
• Drive adoption of advanced verification techniques and Synopsys tooling that improve efficiency and coverage across the Systems Solutions Group
• Contribute to SOC designs that end up in products ranging from autonomous vehicles to next-generation data center processors

What You'll Need

• Bachelor's or Master's in Electronics Engineering or related field with 2 to 5 years of hands-on experience in IP or SOC verification
• Strong working knowledge of SystemVerilog, UVM, and processor-based SOC verification environments
• Experience with VCS, waveform debugging tools, and integrating third-party VIPs like Synopsys VIP into testbenches
• Solid understanding of AXI and AMBA protocol variants, including how they behave under corner cases and error conditions
• Proficiency in scripting with shell, Makefile, or Perl to automate regression flows and post-process simulation results
• Working knowledge of ASIC design flow, RTL design concepts, and how verification fits into the broader chip development lifecycle
• Experience with ARM core verification, USB, PCIe, or MIPI protocols is a strong plus

Who You Are

• You can take a 200-page design spec, identify the five things most likely to break, and build a verification plan around them without being told what to prioritize