RTL (ASIC) Design Engineer

RTL Design Engineer (SDC Constraints) : + : : / We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise in RTL design, timing constraints, and close collaboration with synthesis and STA teams. '96; Design and develop RTL (Verilog/SystemVerilog) for complex ASIC blocks and subsystems '96; Create, review, and maintain SDC constraints (clock definitions, I/O constraints, false paths, multicycle paths, exceptions, etc.) '96; Work closely with synthesis, STA, physical design, and verification teams to achieve timing closure '96; Perform RTL quality checks, linting, and CDC analysis '96; Support timing debugging and constraint optimization across multiple design iterations '96; Participate in architecture discussions and design reviews '96; Ensure deliverables meet performance, power, and area (PPA) goals. '05; & %AA;️ 7+ years of hands-on experience in RTL ASIC design %AA;️ Strong and mandatory expertise in SDC %AA;️ Clocking strategies %AA;️ Timing exceptions %AA;️ Constraint validation and debug %AA;️ Proficiency in Verilog/SystemVerilog %AA;️ Solid understanding of ASIC design flow (RTL → Synthesis → STA → P&R) %AA;️ Experience working with Synopsys tools (DC, PrimeTime – preferred) %AA;️ Strong knowledge of timing concepts and timing closure %AA;️ Excellent debugging and problem-solving skills Experience in low-power design techniques Exposure to CDC/RDC methodologies Experience with complex SoC designs Scripting knowledge (Tcl / Perl / Python) Prior experience working with global or distributed teams