Design Engineer

Position : Design Engineer

Experience : 3 7 Years

Location : Bangalore

Notice Period : immediate / 15 Days NP

Skillset Required:

\n
• Proficient in RTL Verification using SystemVerilog (SV) and UVM .
\n
• Strong knowledge of FPGA Design Flow using VHDL as the RTL language.
\n
• Hands-on experience in developing SV/UVM verification environments .
\n
• Experience with Questa , Modelsim , or similar advanced simulation tools.
\n
• Familiarity with the DO-254 verification process is a strong plus.
\n

\n
• Develop tests and test environments using SystemVerilog UVM for requirement-based testing .
\n
• Create and maintain test plans and self-checking test benches to meet verification criteria and achieve code coverage goals .
\n
• Perform requirement validation , requirement reviews , and test plan reviews .
\n
• Develop or update verification environments at both block-level and system-level .
\n
• Conduct code coverage analysis and ensure verification completeness.
\n

\n
• 3 5 years of industry experience in development, integration, and verification of ASIC/FPGA firmware .
\n