Principal Engineer, Design Verification

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Job Summary

We are seeking a highly experienced Principal Verification Engineer to lead and drive functional verification for complex ASIC/SoC designs. This role requires deep technical expertise, strong architecture-level thinking, strong understanding of Ethernet specifications, and the ability to mentor teams while ensuring delivery of high-quality silicon. The ideal candidate will own verification strategy end-to-end and work closely with design, architecture, and post-silicon teams. The candidate will play a key role in ensuring standards compliance, performance, interoperability and robustness of ethernet products.

Key Responsibilities

Technical Leadership

• Define and own verification strategy and methodology (UVM/SystemVerilog) at IP, subsystem, and SoC levels
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• Thoroughly understand and interpret Ethernet and related protocol specifications (IEEE standards, architecture specs, and micro-architecture documents) and translate them into comprehensive verification plans, assertions, and test scenarios
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• Architect scalable verification environments, reusable VIPs, and checkers
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• Drive coverage-driven verification, including functional, code, and assertion coverage
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• Lead verification planning, testbench architecture, and test plan sign-off
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• Identify, Review and guide complex test scenarios and corner cases
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Execution & Quality

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• Ensure first-pass silicon success through rigorous functional and protocol compliance verification
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• Drive bug triage, root-cause analysis, and closure across IP, Subsystem and SoC levels
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• Define and track verification metrics, quality KPIs, and sign-off criteria
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• Validate performance, stress, and corner scenarios such as congestion, backpressure, and error injection
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• Support emulation, FPGA prototyping, and post-silicon validation for Ethernet bring-up and debug
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Cross-Functional Collaboration

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• Work closely with architecture, RTL, DFT, physical design, firmware, and software teams
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• Provide early verification input during architecture and micro-architecture definition, especially around standards compliance and performance assumptions
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• Collaborate with software teams on driver, firmware, and traffic validation
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Mentorship & Process

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• Mentor and technically guide verification engineers across experience levels
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• Establish and enforce verification best practices and coding standards
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• Drive continuous improvements in verification flows, reuse, and productivity
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Required Qualifications

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• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field from reputed college
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• 10+ years of experience in ASIC/SoC design verification
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• Strong hands-on expertise in SystemVerilog, UVM, and SVA
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• Strong understanding of Ethernet architecture and protocols (MAC, PCS, PHY interfaces)
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days