Senior RTL Design Engineer

Purpose:

LTSCT’s Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT's Automotive, Industrial, Energy and Telecom infra business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards.

Areas of Responsibilities:

• Contribute to the RTL delivery for a multitude of projects.
\n
• Work closely with system architects to define high level specifications that are implementable and robust, and Interface with verification/validation teams to ensure design quality and robustness.
\n
• Build strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones.
\n
• Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips.
\n
• Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence.
\n

Qualifications:

\n
• At least 4+years of experience in related domains and have working knowledge.
\n
• Degree in Electrical Engineering or Computer Science, with 7+ years of experience on IP/Sub-System RTL Design.
\n
• Experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
\n
• Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.
\n
• Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.
\n
• Experience and knowledge of Verilog, System Verilog, C/C++, Shell.
\n
• Good knowledge in scripting like Perl, TCL or Python is a plus.
\n
• Proficiency in Metric Driven Verification concepts, functional and code coverage.
\n
• Expertise in directed and constrained random methodologies.
\n
• Good knowledge of formal verification methodologies and assertions.
\n
• Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
\n
• Excellent written and verbal communication skills.
\n
• Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies.
\n
• Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must.
\n
• Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems