Job Description
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"The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools.
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The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF.
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Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable
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Must be proactive, collaborative and detail-oriented capable of exercising independent judgment
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The engineer with experience on debug and root cause the problem in simulation failures
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Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills."
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