RTL Engineer

We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.

Our current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.

If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.

Looking forward to seeing many of you take this step

Minimum requirements:

• B.S. (or M.S.) in Electrical/Electronics/Computer Engineering or related discipline.
• 5+years of handson RTL design experience on highperformance SoCs, preferably MCUs or wireless connectivity devices.
• Strong proficiency in SystemVerilog or VHDL; demonstrated ability to write clean, synthesizable, and testable RTL.
• Deep understanding of digital design fundamentals: pipelining, statemachine design, bus protocols (AHB/APB/AXI), FIFO, arbitration, and clock domain crossing.
• Experience with synthesis tools (DC, Design Compiler, Innovus) and static timing analysis; ability to meet tight performance and power targets.
• Proven track record in lowpower RTL techniques (clock gating, powerdomain isolation, dynamic voltage/frequency scaling).
• Familiarity with verification flow (UVM, simulation, coverage) to effectively collaborate with DV teams.
• Advanced scripting/automation skills (tcl, perl, python, Bash) for flow automation and CI/CD pipelines.
• Excellent written and verbal communication; strong stakeholdermanagement skills across global functional teams.
• Demonstrated ability to lead design efforts, meet aggressive schedule milestones, and mentor junior engineers.

Preferred qualifications:

• Define and implement RTL architecture for complex SoCs, selecting appropriate coding styles, clocking strategies, and lowpower techniques.
• Develop and maintain synthesizable SystemVerilog/VHDL code for digital blocks (core, peripherals, interfaces, DMA, etc.).
• Create and own RTL simulation and synthesis testbenches, running regression to verify functional correctness and timing closure.
• Collaborate with verification engineers to ensure comprehensive test coverage, resolve RTL bugs, and support presilicon validation.
• Perform timing analysis, constraint development (SDC), and STA, iterating on RTL to meet clockfrequency, setup/hold, and power budgets.
• Lead poweraware design techniques (clock gating, power domains, voltage scaling) and ensure compliance with lowpower specifications.
• Participate in design reviews, providing clear documentation of design decisions, tradeoffs, and risk assessments.
• Drive RTL quality improvement by establishing coding guidelines, linting policies, and bestpractice checklists.
• Mentor junior RTL designers, fostering a culture of code quality, continuous learning, and knowledge sharing.
• Work with the EDA team to evaluate and integrate new synthesis, placeandroute, and static timing tools, improving flow efficiency.
• Support postsilicon bringup and bringdown activities, assisting software/ROM teams with RTLrelated debug and performance tuning.