Formal Verification Engineer

Formal Verification Engineer

Experience : 4 to 12 Years

Location : Bangalore

Job Description

\n
• Responsible for developing and executing formal verification strategies for IP and SoC blocks.
\n
• Write and prove assertions using SystemVerilog Assertions (SVA) or PSL.
\n
• Use tools like JasperGold, VC Formal, or OneSpin to verify complex designs.
\n
• Collaborate with design and DV teams to integrate formal early in the cycle.
\n
• Identify corner-case bugs that are hard to detect via simulation.
\n
• Perform connectivity, X-check, and equivalence checking using formal apps.
\n
• Debug failures and analyze root causes efficiently.
\n
• Drive closure with coverage and waiver management.
\n
• Automate formal flows using scripting (Python, Perl, or Tcl).
\n
• Document verification plans, results, and sign-off reports.
\n

About Company

ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.