Design Verification Lead

This role is for one of the Weekday's clients

Salary range: Rs 3500000 - Rs 6000000 (ie INR 35-60 LPA)

Experience: 7+ yrs

Location: Bengaluru

Job Type: Full-Time

We are looking for a skilled Design Verification Engineer with strong expertise in SystemVerilog (SV) and UVM methodologies to verify complex IP and SoC designs. The ideal candidate will have hands-on experience in building robust verification environments, validating industry-standard protocols, and ensuring comprehensive functional coverage across the verification lifecycle.

In this role, you will collaborate with design and architecture teams to develop scalable verification solutions, execute simulation-based verification, and contribute to the successful delivery of high-quality semiconductor products.

Requirements

Key Responsibilities

• Develop and execute comprehensive verification plans based on functional and design specifications.
• Build, maintain, and enhance reusable verification environments using SystemVerilog and UVM methodologies.
• Verify complex IP and SoC designs supporting industry-standard protocols such as PCIe, AXI, AMBA, DDR, USB, Ethernet, MIPI, RISC-V, or similar interfaces.
• Set up, execute, and debug functional and gate-level simulations to identify and resolve design issues.
• Develop regression environments and automate verification flows to improve verification efficiency.
• Perform coverage analysis, identify coverage gaps, and drive functional and code coverage closure.
• Integrate, configure, and validate third-party Verification IPs (VIPs) within verification environments.
• Collaborate closely with design, architecture, and cross-functional teams to debug issues and ensure design quality.
• Participate in verification reviews, defect analysis, and continuous improvement of verification methodologies.
• Contribute to achieving verification milestones while maintaining high quality and project timelines.

What Makes You a Great Fit

• Strong hands-on expertise in SystemVerilog (SV) and UVM for IP and SoC verification.
• Proven experience verifying industry-standard protocols such as PCIe, AXI, AMBA, DDR, USB, Ethernet, MIPI,or RISC-V.
• Experience executing multiple IP or SoC verification projects across the complete verification lifecycle.
• Solid understanding of functional and gate-level simulation, debugging techniques, and regression management.
• Expertise in developing reusable verification environments and scalable automation frameworks.
• Experience translating functional specifications into structured verification plans and test strategies.
• Strong knowledge of coverage-driven verification, coverage analysis, and closure methodologies.
• Hands-on experience evaluating, integrating, and debugging third-party Verification IPs (VIPs).
• Excellent analytical, debugging, and problem-solving skills with attention to detail.
• Effective communication and collaboration skills with the ability to work in cross-functional engineering teams.