Design verification engineer

This role is for one of the Weekday's clients

Salary range: Rs 500000 - Rs 2500000 (ie INR 5 - 25 LPA)

Min Experience: 2+ years

Location: Bengaluru

JobType: full-time

We are seeking a highly motivated Design Verification Engineer with 2-10 years of experience in functional verification of complex digital designs. The ideal candidate will have strong expertise in DDR verification and UVM-based verification methodologies, along with a solid understanding of modern verification flows. You will be responsible for developing robust verification environments, executing comprehensive test plans, and ensuring high-quality silicon by identifying and resolving design issues early in the development cycle.

Requirements

Key Responsibilities

• Develop and execute verification plans for complex digital IPs and SoCs with a focus on DDR subsystems.
• Build, enhance, and maintain reusable verification environments using the Universal Verification Methodology (UVM).
• Design and implement constrained-random, directed, and coverage-driven test cases to validate functional correctness.
• Develop verification components such as drivers, monitors, scoreboards, sequences, and functional coverage models.
• Perform regression testing, analyze failures, debug design and verification issues, and work closely with design teams to resolve defects.
• Ensure complete functional coverage and contribute to coverage closure using code, assertion, and functional coverage metrics.
• Collaborate with architects, RTL designers, firmware teams, and system engineers to understand design specifications and verification requirements.
• Participate in design reviews, verification planning, and debugging sessions throughout the product development lifecycle.
• Automate verification tasks, improve regression efficiency, and enhance verification productivity through scripting and process improvements.
• Document verification strategies, test plans, and verification results while adhering to engineering best practices.

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
• 2-10 years of hands-on experience in ASIC or SoC Design Verification.
• Strong expertise in DDR protocol verification, including experience verifying DDR controllers, PHYs, or memory interfaces.
• Proficiency in developing verification environments using UVM.
• Strong understanding of functional verification concepts including constrained-random verification, assertions, scoreboards, checkers, and coverage-driven verification.
• Experience with simulation, debugging, regression execution, and waveform analysis.
• Familiarity with verification planning, testbench architecture, and verification closure methodologies.
• Excellent analytical, debugging, and problem-solving skills.
• Strong communication and collaboration abilities in cross-functional engineering teams.

Must-Have Skills

• DDR Verification
• Universal Verification Methodology (UVM)
• Functional Verification
• ASIC/SoC Verification
• Constrained-Random Verification
• Coverage-Driven Verification
• Verification Planning
• Regression Testing
• Debugging and Waveform Analysis

Good-to-Have Skills

• SystemVerilog
• PCIe Protocol Verification
• Assertions (SVA)
• AMBA protocols (AXI, AHB, APB)
• Perl, Python, or Tcl scripting
• Formal Verification concepts
• Low-power verification (UPF/CPF)
• Continuous Integration (CI) workflows