Posted 15 July, 2026
Functional Verification Engineer
ACL Digital
Bengaluru, KA, IN
Full Time
Reference: eec859189634ad3a
Job Description
Job Title: Functional Verification Engineer
\nLocation: Bangalore
\nExperience: 4+ Years
\nJob Type: Full-time
\nIndustry: Semiconductor / VLSI / ASIC Design
\nEducation: B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering
\nJob Description:
\nWe are seeking a skilled and detail-oriented Functional Verification Engineer to be part of our IP/SoC verification team. The candidate will be responsible for verifying complex digital designs using industry-standard methodologies to ensure functional correctness and high-quality silicon delivery.
\nKey Responsibilities:
\n- \n
- Develop and execute verification test plans based on design specifications and architecture. \n
- Design and implement testbenches using SystemVerilog and UVM methodology. \n
- Create constrained-random and directed test cases. \n
- Build verification components (agents, monitors, scoreboards, checkers). \n
- Perform coverage analysis (code and functional) and close coverage gaps. \n
- Debug simulation failures and work closely with design and architecture teams. \n
- Conduct regressions and analyze results for functional and performance issues. \n
- Document test plans, verification environments, and test results. \n
- Participate in design and verification reviews. \n
Required Skills:
\n- \n
- 4+ years of hands-on experience in functional verification of IP/SoC. \n
- Strong knowledge and working experience with SystemVerilog and UVM . \n
- Familiarity with RTL design (Verilog/VHDL). \n
- Experience in coverage-driven verification, assertions, and functional coverage closure. \n
- Proficient in using simulators like VCS, Questa, or Incisive. \n
- Good scripting skills in Perl, Python, or Shell for automation. \n
- Strong debugging skills using simulation waveform viewers. \n
- Good understanding of common protocols such as AXI, AHB, APB, PCIe, USB, etc \n
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