SOC Engineering, Staff Engineer - RTL Design

Job Title:

• RTL Design Engineer, Staff Level - SoC Design

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in RTL design knowing that clean code at the front end saves weeks of pain downstream. You have learned the hard way that a missed clock domain crossing or an unchecked reset scheme does not just slow synthesis, it breaks trust with the implementation team counting on your work. You think in terms of signoff quality before tape-out pressure hits, not after.

You are the engineer who opens Spyglass before the design review, not during integration panic. When you see a CDC violation, you do not just waive it, you trace it back to the architecture decision that caused it and you ask whether that decision still makes sense. You have written SDC constraints that actually reflect design intent, not just pass a tool check.

Working across subsystems and full SOCs does not intimidate you. You have integrated third-party IP, debugged synthesis mismatches at 2 a.m., and run formality enough times to know when the issue is in the script versus the RTL. You care about the quality of what you hand off because you have been on the receiving end of messy handoffs before.

At Synopsys, you will work on real customer SOC projects that ship into production, alongside a team that takes signoff seriously.

What You'll Be Doing

• Run RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SOC designs
• Develop and validate timing constraints in SDC format for synthesis and static timing analysis, ensuring design intent is captured correctly
• Execute preliminary synthesis runs using Design Compiler to verify RTL synthesizability, identify timing bottlenecks, and catch issues before implementation
• Perform formal equivalence checking with Formality between RTL and gate-level netlists to ensure functional correctness through the flow
• Integrate customer and third-party IP into subsystem and SOC-level RTL designs, managing hierarchy, interfaces, and design-for-test requirements
• Debug and resolve design issues related to clock domain crossings, reset schemes, and RTL coding violations in collaboration with architecture and verification teams
• Deliver signoff-quality RTL and constraint packages to implementation teams on customer projects ranging from startups to industry leaders

The Impact You Will Have

• Enable faster, cleaner SOC tape-outs by catching design issues at the RTL stage instead of during physical implementation
• Reduce downstream respins and schedule risk by delivering synthesis-ready, formally verified RTL with accurate timing constraints
• Improve design quality and customer confidence across Synopsys System Solutions Group engagements spanning commercial and government projects
• Build reusable signoff methodologies and constraint templates that scale across multiple customer programs and technology nodes
• Strengthen cross-functional collaboration by providing implementation teams with RTL they can trust and constraints that reflect real design intent
• Contribute to the successful delivery of complex, high-stakes SOC projects where your signoff rigor directly affects product success
• Help define best practices for RTL quality and static verification within a team working on some of the industry's most challenging semiconductor designs

What You'll Need

• Bachelor's or Master's in Electronics Engineering, Electrical Engineering, or related field
• 4+ years of hands-on experience in RTL design, verification, or SOC integration
• Proven experience using Spyglass or equivalent tools for LINT, CDC, and RDC static verification
• Strong working knowledge of SDC timing constraint development and synthesis flows using Design Compiler or similar tools
• Solid understanding of clock domain crossing, reset domain crossing, and common RTL design pitfalls that affect timing and functionality
• Experience running formal equivalence checking with Formality or equivalent tools, experience with SystemVerilog and Verilog RTL coding is a plus

Who You Are

• You can look at a CDC violation report and trace the root cause back to a clocking architecture decision without getting lost in the noise
• You write timing constraints that capture what the design actually needs, not just what makes the tool happy, and you can explain the difference