System-on-Chip Design Engineer

System-on-Chip (SoC) Design Engineer

Location: Bengaluru, India

Experience: 5–12 Years

Role:

Design and implement high-performance SoC subsystems from microarchitecture to silicon. Collaborate with architecture, verification, DFT, STA, and physical design teams to deliver high-quality, PPA-optimized RTL for next-generation AI, Compute, and Networking SoCs.

Responsibilities

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• Develop microarchitecture and RTL using Verilog/SystemVerilog.
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• Design datapaths, pipelines, FSMs, memory interfaces, and control logic.
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• Integrate SoC IPs and AMBA-based interconnects (AXI/AHB/APB).
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• Optimize designs for Power, Performance, and Area (PPA).
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• Drive RTL quality through Lint, CDC/RDC, synthesis, and debug.
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• Support timing closure, verification, and silicon bring-up.
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Required Skills

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• 5–12 years of ASIC/SoC RTL Design experience.
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• Strong microarchitecture and RTL design expertise.
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• Proficiency in Verilog/SystemVerilog and ARM-based SoC architecture.
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• Experience with AMBA protocols, high-speed interfaces, and Synopsys Design Compiler.
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• Hands-on with Lint, CDC/RDC, VCS/Xcelium/Questa, and Python/Tcl/Perl scripting.
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• Exposure to advanced nodes (7nm/5nm/3nm) is a plus.
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