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Posted 12 June, 2026

Lead Analog Mixed-Signal Design Engineer

Advanced Micro Devices, Inc
Bengaluru, KA, IN Full Time
Reference: ef68d74d10f2bedb

Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing...

Job Description



WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.



PREFERRED EXPERIENCE:

  • Analog/Mixed signal design lead with 8+ years of professional experience in the semiconductor industry with focus on analog/mixed signal silicon IP design and development.
  • Analytical thinking, inventive, and Quality-oriented mindset. Strong and effective technical and management communication at the peer and upward management levels.
  • Hand-on design experience in high-speed serial and/or parallel (memory, SerDes, die-to-die interfaces) PHY/IO designs.
  • Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for IO receiver/transmitter analog-front-end (AFE) and PLL/DLL/clocking (PCIE, USB,…,LPDDR, HBM, gDDR, …, UCIE, …)
  • Design Experience in FinFET nodes such as 16/14/10/7/5/3nm nodes with a solid understanding of transistor device performance and fundamentals
  • A track record of successful design and productization of analog/mixed signal silicon IPs.
  • Direct hands-on experience in the following PHY/IO-AFE/PLL/Clocking circuits architecture and design. In-depth knowledge of analog, digital, and semi-digital circuit architecture
  • Experience in high-speed custom digital and low power design techniques is highly desirable.
  • knowledge of AMS EDA industry-standard tools and best-in-class design practices/methodologies for analog/mixed signal design. Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture/virtuoso, Spectre/HSPICE/other circuit simulation tools
  • Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic environment.
  • strong initiative and ownership. Seek help proactively as well as share and pass on knowledge
  • Master’s degree in electrical engineering. PhD is preferred
  • KEY RESPONSIBILITIES:

  • Lead and manage a team of analog/mixed signal silicon designers
  • Responsibilities include detailed circuit design schedule planning, work breakdown, design tasks assignments and progress tracking, prioritization
  • Work with project/IP director, and other cross-functional leads, system architects, SOC designers and physical designers to guarantee quality/timely deliverables meeting schedule and technical requirements
  • Contribute to the definition of analog circuit architecture for the various AMS blocks.
  • Work with other design functions domains across different geographies and time zones, to ensure successful cross-functional team engagement and high-quality execution
  • Ensure quality of work within schedule and mitigate overall risk.
  • Proven Track record of successfully taking designs to production
  • Contribute to the definition of AMS design flows toward improving team productivity, efficiency and quality of execution. Influence development of AMS design workflows and methodology for best in-class/best PPA circuits designs.
  • Complete bottom-up schedule planning and manage analog/mixed circuit design/verification activities guaranteeing AMS IP/sub-blocks designs meets performance, power, reliability and timing requirements.
  • Work closely with the layout design teams to deliver the DRC rules compliant physical design GDSII
  • Deliver AMS Block production/bench-level test plans for post-silicon characterization/validation. Enable/Support Post-Silicon teams’ activities toward validation and characterization of mixed IP (Performance, Power, Functionality, ..) ensuring production silicon meets all committed design and compliance specifications.
  • #LI-PK2



    Benefits offered are described: AMD benefits at a glance.

    AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

    AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

    This posting is for an existing vacancy.

    PREFERRED EXPERIENCE:

  • Analog/Mixed signal design lead with 8+ years of professional experience in the semiconductor industry with focus on analog/mixed signal silicon IP design and development.
  • Analytical thinking, inventive, and Quality-oriented mindset. Strong and effective technical and management communication at the peer and upward management levels.
  • Hand-on design experience in high-speed serial and/or parallel (memory, SerDes, die-to-die interfaces) PHY/IO designs.
  • Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for IO receiver/transmitter analog-front-end (AFE) and PLL/DLL/clocking (PCIE, USB,…,LPDDR, HBM, gDDR, …, UCIE, …)
  • Design Experience in FinFET nodes such as 16/14/10/7/5/3nm nodes with a solid understanding of transistor device performance and fundamentals
  • A track record of successful design and productization of analog/mixed signal silicon IPs.
  • Direct hands-on experience in the following PHY/IO-AFE/PLL/Clocking circuits architecture and design. In-depth knowledge of analog, digital, and semi-digital circuit architecture
  • Experience in high-speed custom digital and low power design techniques is highly desirable.
  • knowledge of AMS EDA industry-standard tools and best-in-class design practices/methodologies for analog/mixed signal design. Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture/virtuoso, Spectre/HSPICE/other circuit simulation tools
  • Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic environment.
  • strong initiative and ownership. Seek help proactively as well as share and pass on knowledge
  • Master’s degree in electrical engineering. PhD is preferred
  • KEY RESPONSIBILITIES:

  • Lead and manage a team of analog/mixed signal silicon designers
  • Responsibilities include detailed circuit design schedule planning, work breakdown, design tasks assignments and progress tracking, prioritization
  • Work with project/IP director, and other cross-functional leads, system architects, SOC designers and physical designers to guarantee quality/timely deliverables meeting schedule and technical requirements
  • Contribute to the definition of analog circuit architecture for the various AMS blocks.
  • Work with other design functions domains across different geographies and time zones, to ensure successful cross-functional team engagement and high-quality execution
  • Ensure quality of work within schedule and mitigate overall risk.
  • Proven Track record of successfully taking designs to production
  • Contribute to the definition of AMS design flows toward improving team productivity, efficiency and quality of execution. Influence development of AMS design workflows and methodology for best in-class/best PPA circuits designs.
  • Complete bottom-up schedule planning and manage analog/mixed circuit design/verification activities guaranteeing AMS IP/sub-blocks designs meets performance, power, reliability and timing requirements.
  • Work closely with the layout design teams to deliver the DRC rules compliant physical design GDSII
  • Deliver AMS Block production/bench-level test plans for post-silicon characterization/validation. Enable/Support Post-Silicon teams’ activities toward validation and characterization of mixed IP (Performance, Power, Functionality, ..) ensuring production silicon meets all committed design and compliance specifications.
  • #LI-PK2

    Benefits offered are described: AMD benefits at a glance.

    AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

    AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

    This posting is for an existing vacancy.

This listing expired on 15 Jun. Applications are no longer accepted.

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