Senior Engineer - SOC Verification

Position Overview:

We are looking for a highly experienced Senior Engineer in SoC Design Verification to join our dynamic team and contribute to the development of cutting-edge SoC solutions.

As a Senior Engineer in SoC Design Verification, you will play a key role in leading the SV/UVM based Subsystem and SoC verification strategy, planning, and execution for complex SoC projects. You will collaborate closely with cross-functional teams to ensure the highest quality and performance standards for our SoC products. This role requires deep technical expertise, leadership skills, and a passion for solving challenging verification problems.

Key Responsibilities :

• Architect and develop reusable testbenches and Verification IP (VIP) using SystemVerilog and UVM to create scalable verification environments from scratch.
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• Drive coverage closure , ensuring thorough functional coverage and code coverage across all SoC components.
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• Implement and manage SV assertions and coverage-driven verification strategies to validate designs effectively.
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• Utilize formal verification methods and tools to verify complex blocks and subsystems, complementing simulation-based verification.
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• Develop comprehensive test plans and ensure their execution at the block, subsystem, and full-chip levels.
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• Lead debug activities and identify design and verification bottlenecks early in the development cycle.
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• Mentor junior engineers on best practices for SV/UVM, reusable verification, assertions, and coverage analysis.
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• Collaborate with design, architecture, and system-level teams to define and implement verification strategies that meet stringent quality and performance goals.
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• Drive continuous improvement of verification methodologies and tools to enhance team efficiency and quality.
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Requirements :

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• 3+ years of experience in ASIC/SoC verification, specializing in SystemVerilog (SV) and Universal Verification Methodology (UVM) .
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• Proven expertise in building reusable verification environments and VIP development from the ground up.
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• Strong experience with coverage-driven verification , including functional and code coverage analysis and closure.
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• Expertise in writing and debugging SV assertions and applying formal verification techniques.
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• Hands-on experience with the full verification lifecycle, from test plan creation to regression analysis and closure.
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• Strong problem-solving, debugging, and analytical skills in a fast-paced environment.
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• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
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Nice to Have :

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• Experience with Pre-Silicon Validation , including test environment setup and validation strategies.
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• Proficiency in FPGA prototyping and hardware emulation to complement verification strategies.
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• Familiarity with ARM-based SoC architectures and high-performance SoC designs for applications such as IP Cameras, automotive, or AI/ML.
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• Knowledge of low-power verification and formal verification techniques .
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Why Join Us? :

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• Be part of a team pushing the boundaries of ASIC SoC design.
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• Work on cutting-edge technology in a collaborative and innovative environment.
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• Competitive salary and benefits.
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• Opportunities for growth and leadership within the company.