Advantest 93K Senior RF Test Engineer

The ideal candidate will be responsible for RF /Mixed Signal test program development, validation, characterization, production support, and yield improvement for RF and mixed-signal semiconductor devices. The role spans all phases of the test engineering lifecycle — from test plan development and hardware design through software development, silicon bring-up, debug, correlation, and sustaining support.\nThe engineer will work within a high-performing global cross-functional team and will interface directly with design, characterization, product engineering, and customer teams. As an early member of Anora's expanding Bangalore center, this position offers career growth and visibility unmatched in larger organizations.\n\nKey Responsibilities ATE Test Program Development — Advantest 93K\n• Develop, debug, and maintain RF & Mixed Signal production test programs on the Advantest V93000 platform.\n• Design and implement RF test methodologies for devices such as LNAs, PAs, RF switches, transceivers, mixers, synthesizers, and wireless connectivity ICs using 93K test resources.\n• Write test flows and Test Methods using the 93K test framework (C++/Java-based); manage revision control and participate in code reviews.\n• Develop and validate test limits based on datasheet specifications and characterization data.\n• Perform test time optimization using parallelism, concurrent testing, and time-domain multiplexing techniques\n• Perform device characterization, correlation, and production release activities.\n• Develop and optimize test solutions to improve test coverage, reduce test time, and maximize production yield.\n• Analyze test data and identify root causes of yield excursions and failures.\n• Support NPI (New Product Introduction) activities from characterization through high-volume manufacturing.\n• Develop and maintain hardware interface documentation, test specifications, and release packages.\n• Troubleshoot ATE hardware, RF instrumentation, load boards, and probe cards.\n• Participate in GR&R, correlation studies, guard-banding, and test limit optimization.\n• Drive continuous improvement initiatives related to test efficiency, quality, and manufacturing productivity.\n• Provide technical leadership and mentoring to junior test engineers.\nMixed-Signal Test Engineering\n• Develop ATE-based test solutions for ADCs, DACs, LDOs, op-amps, comparators, and voltage references on 93K.\n• ADC/DAC: SNR, SFDR, THD, DNL, INL, ENOB measurements using coherent and non-coherent DSP methods.\n• LDO/PMIC: Load regulation, line regulation, PSRR, transient response, quiescent current.\n• Op-Amp/Comparator: Offset voltage, CMRR, PSRR, slew rate, bandwidth, noise spectral density.\n• Implement DSP-based signal analysis including FFT, windowing, and curve-fitting algorithms for analog characterization.\n• Ensure measurement accuracy and guard-banding through careful noise floor analysis and DUT board design.\nHardware — Load Board & Interface Design\n• Design, review, and debug DUT load boards (DIBs) for the Advantest 93K including analog signal routing, power planes, bypass/decoupling, and RF shielding.\n• Define and validate analog/power interface circuits: current sense resistors, bulk capacitors, inductors, current mirrors.\n• Perform load board schematic review and layout guideline definition in collaboration with PCB design teams.\n• Characterize load board parasitic (trace inductance, capacitance) and apply compensation in the test plan.\n• Set up and validate contactors, sockets, and probe cards; perform contact resistance and leakage checks.\nTest Correlation & Characterization\n• Perform ATE-to-bench correlation for all critical parameters; analyze and reduce correlation deltas.\n• Support product characterization and process corner analysis (SS, TT, FF) across temperature and voltage.\n• Execute guard-band analysis and set production test limits to balance yield and quality (DPPM targets).\n• Analyze parametric distributions, generate SPC charts, and track yield trends over product lifetime.\nSustaining & Yield Improvement\n• Investigate and resolve production yield excursions, test escapes, and outlier failures.\n• Perform failure analysis in collaboration with design and product engineering teams.\n• Drive continuous test time reduction and hardware cost optimization for high-volume production.\n• Maintain test program and documentation changes through a formal ECO / change control process.\n\nRequirements & Skills • Bachelor's or Master’s degree in Electronics, Electrical, or Instrumentation Engineering.\n• 8–10 years of semiconductor test engineering experience.\n• Strong expertise in Advantest V93000 (93K) ATE platform.\n• Experience with SmarTest development environment.\n• Strong understanding of RF fundamentals and measurement techniques.\n• Experience testing wireless technologies such as Bluetooth, Wi-Fi, Cellular, GNSS, UWB, or similar RF products.\n• Knowledge of RF parameters including Gain, Output Power (Pout), Noise Figure (NF), EVM, ACLR/ACPR, Phase Noise, S-Parameters, IP3, Harmonics and Spurious Measurements\n• Experience with RF calibration, de-embedding, and correlation methodologies.\n• Strong debugging and problem-solving skills.\n• Ability to analyze large datasets and identify yield/performance trends.\nATE Platform & Test Environment\n• Experience with Advantest instruments such as Pin Scale / Wave Scale RF, FVI16, AVI64, PS1600, DPS128, etc.).\n• Programming experience in C/C++, Java, Python, or Perl.\n• Familiarity with semiconductor characterization tools and data analysis software.\n• Understanding of statistical process control (SPC), DOE, and yield enhancement methodologies.\n• Experience with probe and final test environments.\n• Knowledge of mixed-signal and high-speed digital testing is a plus.\n• Version control using SVN/Git.\nTools & Systems\n• Experience with EDA tools for schematic review (Allegro, Altium, or KiCad).\n• Familiarity with JIRA, Confluence, or equivalent tools for project tracking and documentation.\n• Understanding of semiconductor manufacturing flow: wafer sort, final test, burn-in, and qualification (AEC-Q100 / JEDEC).\nSoft Skills & Attributes\n• Strong debugging and analytical mindset with systematic root-cause analysis approach.\n• Clear written and verbal communication skills for cross-functional collaboration with global teams.\n• Self-driven, proactive, and able to manage multiple tasks in a fast-paced environment.\n• Open-minded team player with a 'can-do' attitude and willingness to take ownership.\n\nWhy Join Anora?

• Work alongside world-class semiconductor test engineers with decades of domain expertise.\n• Exposure to a broad spectrum of cutting-edge mixed-signal and power IC programs.\n• Global cross-functional collaboration with design, validation, and customer teams across USA, Europe, and Asia.\n• International travel and customer-site engagement opportunities.\n• Fast-track career growth is a key contributor in a rapidly expanding global organization.\n • Innovative, inclusive work culture that rewards initiative, quality, and continuous learning.