Analog Mixed Signal Verification

Job description\nDear Candidate,\nGreetings from TATA Consultancy Services!!\nThank you for expressing your interest in exploring a career possibility with the TCS Family.\nHiring For:- Analog Mixed Signal Verification\nLocation: Bangalore / Hyderabad / Noida / Ahmedabad/ Chennai/ Mumbai/ Pune\nExperience: 3-9 years\n\nRole Overview\nThe Analog Mixed-Signal (AMS) Verification Engineer is responsible for functional, performance, and robustness verification of analog and mixed-signal IPs, subsystems, and SoCs. The role bridges analog and digital domains using mixed-signal simulation, behavioral modeling, assertions, coverage, and post-silicon correlation to ensure first-pass silicon success. The engineer works closely with analog designers, digital verification teams, layout, and silicon validation teams.\nCore Responsibilities (All Levels)\nDevelop and execute AMS verification plans for IP, subsystem, and SoC levels\nBuild mixed-signal verification environments combining analog and digital domains\nDevelop behavioral models using Verilog-AMS, Wreal, or real-number modeling (RNM)\nRun and analyze mixed-signal simulations for functionality, timing, and performance\nValidate PLL lock, jitter, noise, power-up/down behavior, and corner sensitivity\nCollaborate with analog and digital teams to debug cross-domain issues\nSupport post-layout, post-silicon validation, and silicon-to-simulation correlation\nAutomate regressions, analysis, and reporting using scripts\nSenior AMS Verification Engineer 3 to 5 Years\nExecute block-level AMS verification under guidance\nRun mixed-signal simulations for basic AMS IPs such as comparators and bandgaps\nAssist in developing Verilog-AMS / Wreal models for analog blocks\nAnalyze waveforms and debug functional issues\nSupport regression runs and basic coverage collection\nLead AMS Verification Engineer – 6 to 9 Years\nOwn IP or subsystem-level AMS verification from plan to signoff\nArchitect mixed-signal verification environments using SV/UVM with AMS integration\nDevelop assertions, checkers, and functional coverage for AMS behaviors\nVerify performance metrics such as jitter, phase noise, lock time, INL/DNL, and PSRR\nWork closely with analog designers on debug and design trade-offs\nSupport low-power, multi-mode, and post-layout verification activities\nMember Technical Staff / Principal AMS Verification Engineer – 10+ Years\nDefine AMS verification strategy and methodology for complex SoCs\nOwn full-chip AMS verification and signoff across PVT and stress scenarios\nDrive development of reusable AMS frameworks and robust behavioral models\nLead silicon bring-up support and silicon-to-simulation correlation efforts\nGuide cross-domain debug involving analog, digital, and system interactions\nMentor AMS verification engineers and review verification quality\nInterface with customers, architects, and EDA vendors on AMS verification topics\nTools & Skills\nAMS Simulation: Cadence Xcelium AMS, Spectre, AMS Designer\nModeling: Verilog-AMS, Wreal, Real Number Modeling (RNM)\nDigital Verification: SystemVerilog, UVM, UVM-AMS (as applicable)\nDomains: PLL, SerDes, DDR PHY, ADC/DAC, LDO, Bandgap\nPost-Silicon: Lab data analysis, silicon correlation\nAutomation & Analysis: Python, MATLAB