Analog Mixed-Signal Design Verification Engineer

Job DescriptionJob Function
Work on functional verification of analog and mixed-signal IPs, including SERDES, sensors, and beyond. The candidate will collaborate with IP design teams and other verification teams, utilizing and enhancing both established and emerging digital verification methodologies and processes. Responsibilities span the full verification lifecycle—from understanding specifications and developing test plans, to achieving coverage closure and supporting post-silicon debug—to ensure high-quality and efficient pre-silicon verification, ultimately delivering robust silicon products.
Skills/Experience
•Quick learner with strong critical thinking and creative problem-solving skills.
•Solid knowledge in ASIC verification flow, digital design, and UVM-based design verification methodologies.
•Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
•Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
•Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers, and checkers development, to test suite building to meet functional and code coverage goals,
•3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, MIPI etc.
•Power-aware simulations and gate level simulations is a plus.
•Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.
•Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus.
•Familiar with programming languages: C, C++, and/or SystemC is a plus.
RequirementResponsibilities
•Work in Verification of IP’s in UVM-based verification environment.
•Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals
•Apply wide range of Digital and/or AMS DV skills to help and support IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
•Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.
•Contribute to continuous improving on DV process for better quality and efficiency through methodology and process improvements